1. Technical Field
The present invention relates to a system and method for efficiently testing segment lookaside buffer (SLB) and translation lookaside buffer (TLB) cells during processor design verification and validation. More particularly, the present invention relates to a system and method for re-executing a test case and modifying the test case's effective addresses, effective segment identifiers, and virtual segment identifiers in order to fully test each bit in a processor's SLB and TLB cells.
2. Description of the Related Art
Processor testing tools exist whose goal is to generate the most stressful test case for a processor. In theory, the generated test case should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test cases.
Verifying and validating a processor using test cases typically includes three stages, which are 1) test case build stage, 2) test case execution stage, and 3) validation and verification stage. While building a virtual mode test case, a test case generator builds a segment lookaside buffer (SLB) and a translation lookaside buffer (TLB) for translating addresses. A challenge found is that existing art does not provide predictable coverage of the bits included in the SLB and the TLB. In addition, in order to set and unset each bit at least once in the SLB and TLB, an enormous number of translations in each entry is required, which requires new sets of test cases. Unfortunately, building the test cases is cumbersome, let alone difficult to ensure that each bit is set and unset in each TLB entry and each SLB entry at least once.
Furthermore, the SLB and the TLB have as many as 128 bits in each of many entries. Therefore, a large quantity of test cases, each with different translations, is required to cover each cell. Again, generating more test cases requires more time, which leaves less time available for testing the processor.
What is needed, therefore, is a system and method to efficiently test a processor's segment lookaside buffer and translation lookaside buffer.